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8-channel, high throughput, 24-bit -? adc ad7739 features high resolution adc 24 bits no missing codes 0.0015% nonlinearity optimized for fast channel switching 18-bit p-p resolution (21 bits effective) at 500 hz 16-bit p-p resolution (19 bits effective) at 4 khz on-chip per channel system calibration configurable inputs 8 single-ended or 4 fully differential input ranges +625 mv, 625 mv, +1.25 v, 1.25 v, +2.5 v, 2.5 v 3-wire serial interface spi?, qspi?, microwire?, and dsp compatible schmitt trigger on logic inputs single-supply operation 5 v analog supply 3 v or 5 v digital supply package: 24-lead tssop applications plcs/dcss multiplexing applications process control industrial instrumentation general description the ad7739 is a high precision, high throughput analog front end. true 16-bit p-p resolution is achievable with a total conversion time of 250 s (4 khz channel switching), making it ideally suited to high resolution multiplexing applications. the part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to 15 khz. the analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mv, 1.25 v, and 2.5 v input ranges. it accepts a common-mode input voltage from 200 mv above agnd to av dd C 300 mv. the differential reference input features no-reference detect capability. the adc also supports per channel system calibration options. functional block diagram sclk din dout cs rdy reset serial interface control logic ain4 ain5 ain6 ain7 mux a incom/p0 ain0 ain1 ain2 ain3 reference detect refin(?) refin(+) i/o port sync/p1 clock generator 24-bit - ? adc buffer ad7739 calibration circuitry dgnd dv dd mclkin mclkout agnd av dd 03742-0-001 figure 1. the digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. all interface inputs are schmitt triggered. the part is specified for operation over the extended industrial temperature range of C40c to +105c. other parts in the ad7739 family are the ad7738, ad7734, and ad7732. the ad7738 is similar to the ad7739 but has higher speed (8.5 khz channel switching for 16-bit performance) and higher ain leakage current. the ad7738 multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the adc. the ad7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to 10 v while operating from a single +5 v analog supply. the ad7734 accepts an analog input overvoltage to 16.5 v without degrading the performance of the adjacent channels. the ad7732 is similar to the ad7734, but its analog front end features two fully differential input channels. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2003 analog devices, inc. all rights reserved.
ad7739 rev. 0 | page 2 of 32 table of contents ad7739?specifications.................................................................. 3 timing specifications....................................................................... 6 absolute maximum ratings............................................................ 8 typical performance characteristics ............................................. 9 output noise and resolution specification................................ 10 chopping enabled...................................................................... 10 chopping disabled..................................................................... 11 pin configuration and function descriptions........................... 12 register descriptions ..................................................................... 14 register access............................................................................ 15 communications register......................................................... 15 i/o port register......................................................................... 16 revision register ........................................................................ 16 test register ................................................................................ 16 adc status register................................................................... 17 checksum register..................................................................... 17 adc zero-scale calibration register ..................................... 17 adc full-scale calibration register....................................... 17 channel data registers ............................................................. 17 channel zero-scale calibration registers .............................. 18 channel full-scale calibration registers................................ 18 channel status registers ........................................................... 18 channel setup registers ............................................................ 19 channel conversion time registers ....................................... 20 mode register ............................................................................. 20 digital interface description ........................................................ 22 hardware ..................................................................................... 22 reset ............................................................................................. 23 access the ad7739 registers.................................................... 23 single conversion and reading data ...................................... 23 dump mode................................................................................ 23 continuous conversion mode ................................................. 24 continuous read (continuous conversion) mode .............. 25 circuit description......................................................................... 26 analog inputs.............................................................................. 26 sigma-delta adc....................................................................... 26 chopping ..................................................................................... 26 multiplexer, conversion, and data output timing............... 27 frequency response .................................................................. 28 analog input?s extended voltage range ................................. 29 voltage reference inputs........................................................... 29 reference detect......................................................................... 29 i/o port........................................................................................ 29 calibration................................................................................... 30 adc zero-scale self-calibration ........................................ 30 adc full-scale self-calibration.......................................... 30 per channel system calibration .......................................... 30 outline dimensions ....................................................................... 32 esd caution................................................................................ 32 ordering guide .......................................................................... 32 revision history revision 0: initial version
ad7739 rev. 0 | page 3 of 32 ad7739?specifications table 1. (C40c to +105c; av dd = 5 v 5%; dv dd = 2.7 v to 3.6 v, or 5 v 5%; refin(+) = 2.5 v; refin(C) = 0 v, aincom = 2.5 v; internal buffer on, ain range = 1.25 v; f mclkin = 6.144 mhz; unless otherwise noted.) parameter min typ max nit test conditionscomments adc performance choppin enabled conversion time rate 372 11840 hz configure via conv. time register no missing codes 1, 2 24 bits f t 12 (conversion time t 290 s) output noise see table 4 resolution see table 5 and table 6 integral nonlinearity (inl) 2 5 0.0015 % of fsr offset error (nipolar, bipolar) 3 10 v before calibration offset drift vs. temperature 1 25 nvc ain error 3 0.2 % before calibration ain drift vs. temperature 1 2.5 ppm of fsc positive full-scale error 3 0.2 % of fsr before calibration positive full-scale drift vs. temp. 1 2.5 ppm of fsc bipolar negative full-scale error 4 0.0030 % of fsr after calibration common-mode reection 80 95 db at dc, ain = 1 v power supply reection 70 80 db at dc, ain = 1 v adc performance choppin disabled conversion time rate 737 15133 hz configure via conv. time register no missing codes 1, 2 24 bits f t 12 (conversion time t 290 s) output noise see table 7 resolution see table 8 and table 9 integral nonlinearity (inl) 2 0.0015 % of fsr offset error (nipolar, bipolar) 5 1mv mv before calibration offset drift vs. temperature 1.5 vc ain error 3 0.2 % before calibration ain drift vs. temperature 2.5 ppm of fsc positive full-scale error 3 0.2 % of fsr before calibration positive full-scale drift vs. temp. 2.5 ppm of fsc bipolar negative full-scale error 4 0.0030 % of fsr after calibration common-mode reection 75 db at dc, ain = 1 v power supply reection 65 db at dc, ain = 1 v analo inpts analog input voltage 1, 6 2.5 v range 2.5 v +2.5 v range 0 to +2.5 v 1.25 v range 1.25 v +1.25 v range 0 to +1.25 v 0.625 v range 0.625 v +0.625 v range 0 to +0.625 v ain, aincom common-mode absolute voltage 1 0.2 av dd C 0.3 v analog input slew rate 1, 7 0.5 vconv. time ain absolute voltage 3 v ain, aincom input current 1, 8 1 5 na only one channel, chop disabled
ad7739 rev. 0 | page 4 of 32 parameter min typ max unit test conditions/comments reference inputs refin(+) to refin(?) voltage 1, 9 2.475 2.5 2.525 v noref trigger voltage 0.5 v nore f bit in channel status register refin(+), refin(?) common-mode/ absolute voltage 1 0 av dd v reference input dc current 10 400 a system calibration 1, 11 full-scale calibration limit +1.05 u fs v zero-scale calibration limit ?1.05 u fs v input span 0.8 u fs 2.1 u fs v logic inputs input current r 1 a input current cs r 10 a cs = dv dd ?40 a cs = dgnd, internal pull-up resistor input capacitance 5 pf v t+ 1 1.4 2 v dv dd = 5 v v t? 1 0.8 1.4 v dv dd = 5 v v t+ ? v t? 1 0.3 0.85 v dv dd = 5 v v t+ 1 0.95 2 v dv dd = 3 v v t? 1 0.4 1.1 v dv dd = 3 v v t+ ? v t? 1 0.3 0.85 v dv dd = 3 v mclk in only input current r 10 a input capacitance 5 pf v inl input low voltage 0.8 v dv dd = 5 v v inh input high voltage 3.5 v dv dd = 5 v v inl input low voltage 0.4 v dv dd = 3 v v inh input high voltage 2.5 v dv dd = 3 v logic outputs 12 v ol output low voltage 0.4 v i sink = 800 a, dv dd = 5 v v oh output high voltage 4.0 v i source = 200 a, dv dd = 5 v v ol output low voltage 0.4 v i sink = 100 a, dv dd = 3 v v oh output high voltage dv dd ? 0.6 v i source = 100 a, dv dd = 3 v floating state leakage current r 1 a floating state leakage capacitance 3 pf p0, p1 inputs/outputs leve ls referenced to analog supplies input current r 10 a v inl input low voltage 0.8 v av dd = 5 v v inh input high voltage 3.5 v av dd = 5 v v ol output low voltage 0.4 v i sink = 8 ma, av dd = 5 v v oh output high voltage 4.0 v i source = 200 a, av dd = 5 v
ad7739 rev. 0 | page 5 of 32 parameter min typ max unit test conditions/comments power requirements av dd to agnd voltage 4.75 5.25 v dv dd to dgnd voltage 4.75 5.25 v 2.70 3.60 v av dd current (normal mode) 13.6 16 ma av dd current (reduced power mode) 9.2 11 ma mclk = 4 mhz av dd current (internal buffer off) 8.5 ma dv dd current (normal mode) 13 2.7 3 ma dv dd = 5 v dv dd current (normal mode) 13 1.0 1.5 ma dv dd = 3 v power dissipation (normal mode) 13 85 100 mw power dissipation (reduced power mode) 13 60 70 mw dv dd = 5 v, mclk = 4 mhz power dissipation (reduced power mode) 13 50 mw dv dd = 3 v, mclk = 4 mhz av dd + dv dd current (standby mode) 14 80 a power dissipation (standby mode) 14 500 w 1 specification is not production tested, but is supported by characterization data at initial product release. 2 see typical performance characteristics. 3 specifications before calibration. channel system calibration reduces these errors to the order of the noise. 4 applies after the zero-scale an d full-scale calibration. the negative full-sca le error repres ents the remainin g error after re moving the offset and gain error. 5 specifications before calibration. adc zero-scale self-calibration or channel zero-scale system calibration reduce this error t o the order of the noise. 6 for specified performance. the output data span corresponds to the specified nominal input voltag e range. the adc is functional outside the nominal input voltage range, but the performance might degrade. outside the nominal input voltage range, the ovr bit in the channel status register i s set and the channel data register value depends on the clamp bit in the mode register. see the register and circuit descriptions for details. 7 for specified performance. if the analog input absolute voltage (referred to agnd) changes more than 0.5 v during one conversio n time, the result could be affected by distortion in the input buffer. this limit does not apply to analog input absolute voltages below 3 v. 8 if chopping is enabled or when switchin g between channels, a dynamic current charge s the capacitance of the multiplexer. see t he circuit description for details. 9 for specified performance. part is functional with lower v ref . 10 dynamic current charging the sigma-delt a modulator input switching capacitor. 11 outside the specified calibration range, calibrat ion is possible but the performance may degrade. 12 these logic output levels apply to the mclk out output when it is loaded with a single cmos load. 13 with external mclk, mclkout disabled (clkdis bit set in the mode register ). 14 external mclkin = 0 v or dv dd , digital inputs = 0 v or dv dd , p0 and p1 = 0 v or av dd .
ad7739 rev. 0 | page 6 of 32 timing specifications table 2. (av dd = 5 v 5%; dv dd = 2.7 v to 3.6 v, or 5 v 5%; input logic 0 = 0 v; logic 1 = dv dd ; unless otherwise noted.) 1 parameter min typ max nit test conditionscomments master clock range 1 6.144 mhz 1 4 mhz reduced power mode t 1 50 ns snc pulsewidth t 2 500 ns reset pulsewidth read operation t 4 0 ns cs falling edge to sclk falling edge setup time t 5 2 sclk falling edge to data valid delay 0 60 ns dv dd of 4.75 v to 5.25 v 0 80 ns dv dd of 2.7 v to 3.3 v t 5a 2, 3 cs falling edge to data valid delay 0 60 ns dv dd of 4.75 v to 5.25 v 0 80 ns dv dd of 2.7 v to 3.3 v t 6 50 ns sclk high pulsewidth t 7 50 ns sclk low pulsewidth t 8 0 ns cs rising edge after sclk rising edge hold time t 9 4 10 80 ns bus relinuish time after sclk rising edge rite operation t 11 0 ns cs falling edge to sclk falling edge setup t 12 30 ns data valid to sc lk rising edge setup time t 13 25 ns data valid after sclk rising edge hold time t 14 50 ns sclk high pulsewidth t 15 50 ns sclk low pulsewidth t 16 0 ns cs rising edge after sclk rising edge hold time 1 sample tested during initial release to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. see figure 2 and figure 3. 2 these numbers are measured with the load circuit of figure 4 an d defined as the time reuired for the output to cross the v ol or v oh limits. 3 this specification is relevant only if cs goes low while sclk is low. 4 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit of figu re 4. the measured number is then extrapolated back to remove effects of charging or discharging the 50 pf capacitor. this means that the times uoted in the tim ing specifications are the true bus relinuish times of the part and as such are independent of external bus loading capacitances.
ad7739 rev. 0 | page 7 of 32 dout msb lsb cs t 4 t 5a t 5 t 6 t 7 t 9 t 8 sclk 03742-0-002 figure 2. read cycle timing diagram din msb lsb s clk cs t 11 t 14 t 15 t 16 t 13 t 12 03742-0-003 figure 3. write cycle timing diagram i source (200 p a at dv dd = 5v 100 p a at dv dd = 3v) i sink (800 p a at dv dd = 5v 100 p a at dv dd = 3v) 1.6v t o output pin 50pf 03742-0-004 figure 4. load circuit for access time and bus relinquish time
ad7739 rev. 0 | page 8 of 32 absolute maximum ratings table 3. (t a = 25c, unless otherwise noted.) parameter rating av dd to and, dv dd to dnd C0.3 v to +7 v and to dnd C0.3 v to +0.3 v av dd to dv dd C5 v to +5 v ain, aincom to and C0.3 v to av dd + 0.3 v refin+, refinC to and C0.3 v to av dd + 0.3 v p0, p1 voltage to and C0.3 v to av dd + 0.3 v digital input voltage to dnd C0.3 v to dv dd + 0.3 v digital output voltage to dnd C0.3 v to dv dd + 0.3 v esd rating (esd association human body model, s5.1) 4000 v operating temperature range C40c to +105c storage temperature range C65c to +150c unction temperature 150c tssop package t a thermal impedance 128c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational section of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad7739 rev. 0 | page 9 of 32 typical performance characteristics 16 17 18 19 20 21 22 23 24 25 5 6 7 8 9 101112131415 filter word no missing codes 03742-0-005 chop = 1 figure 5. no missing codes pe rformance, chopping enabled 16 17 18 19 20 21 22 23 24 25 5 6 7 8 9 101112131415 filter word no missing codes 03742-0-006 chop = 0 figure 6. no missing codes performance, chopping disabled ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 200 400 600 800 1000 1200 1400 input frequency (hz) gain (db) 03742-0-007 thd = 110db figure 7. typical fft plot; input sine wave 183 hz,1.2 v peak, ain range 1.25 v, conversion time 397 s, chopping enabled, mclk = 6.144 mhz 8 10 12 14 16 18 20 22 24 10 68 24 0 121416 output data rate (khz) resolution (bits) 03742-0-008 chop = 1 p-p effective (rms) figure 8. typical effective and peak-to-peak resolution; ain voltage = 0 v, ain range 1.25 v, chopping enabled, mclk = 6.144 mhz 8 10 12 14 16 18 20 22 24 10 68 24 0 121416 output data rate (khz) resolution (bits) 03742-0-009 chop = 0 p-p effective (rms) figure 9. typical effective and peak-to-peak resolution; ain voltage = 0 v, ain range 1.25 v, chopping disabled, mclk = 6.144 mhz 60 70 80 90 100 110 120 0 ?0.5 ?1.0 ?1.5 0.5 1.0 1.5 ain differential voltage (v) cmr (db) 03742-0-010 chop = 1 figure 10. typical common-mode rejection vs. ain voltage; ain range 1.25 v, conversion time 397 s, chopping enabled, mclk = 6.144 mhz
ad7739 rev. 0 | page 10 of 32 output noise and reso lution specification the ad7739 can be operated with chopping enabled or disabled, allowing the adc to be programmed to optimize either the offset drift performance or the throughput rate and channel switching time. noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. the ad7739 noise performance depends on the selected chopping mode, the filter word (fw) value, and the selected analog input range. the ad7739 noise will not vary significantly with mclk frequency. chopping enabled the first mode, in which the ad7739 is configured with chopping enabled (chop = 1), provides very low noise with lower output rates. table 4 to table 6 show the ?3 db frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. table 4 shows the typical output rms noise. table 5 shows the typical effective resolution based on rms noise. table 6 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table 4. typical output rms noise in v vs. conversion time and input range with chopping enabled input range rms noise (v) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v, +2.5 v 1.25 v, +1.25 v, 0.625 v, +0.625 v 127 0xff 2689 372 200 1.8 1.1 46 0xae 1001 999 500 2.7 1.7 17 0x91 397 2519 1325 4.8 2.7 10 0x8a 251 3982 2209 9.3 4.7 9 0x89 230 4342 2450 10.8 6.3 2 0x82 84 11838 9500 600 460 table 5. typical effective resolution in bits vs. conversion time and input range with chopping enabled input range effective resolution (bits) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v +2.5 v 1.25 v +1.25 v 0.625 v +0.625 v 127 0xff 2689 372 200 21.4 20.4 21.2 20.2 20.2 19.2 46 0xae 1001 999 500 20.8 19.8 20.5 19.5 19.5 18.5 17 0x91 397 2519 1325 20.0 19.0 19.8 18.8 18.8 17.8 10 0x8a 251 3982 2209 19.0 18.0 19.0 18.0 18.0 17.0 9 0x89 230 4342 2450 18.8 17.8 18.6 17.6 17.6 16.6 2 0x82 84 11838 9500 12.9 11.9 12.4 11.4 11.4 10.4 table 6. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping enabled input range peak-to-peak resolution (bits) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v +2.5 v 1.25 v +1.25 v 0.625 v +0.625 v 127 0xff 2689 372 200 18.6 17.6 18.3 17.3 17.3 16.3 46 0xae 1001 999 500 17.9 16.9 17.6 16.6 16.6 15.6 17 0x91 397 2519 1325 17.1 16.1 16.9 15.9 15.9 14.9 10 0x8a 251 3982 2209 16.2 15.2 16.2 15.2 15.2 14.2 9 0x89 230 4342 2450 16.0 15.0 15.8 14.8 14.8 13.8 2 0x82 84 11838 9500 10.7 9.7 9.7 8.7 8.7 7.7
ad7739 rev. 0 | page 11 of 32 chopping disabled the second mode, in which the ad7739 is configured with chopping disabled (chop = 0), provides faster conversion time while maintaining high resolution. table 7 to table 9 show the ?3 db frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. table 7 shows the typical output rms noise. table 8 shows the typical effective resolution based on the rms noise. table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. the peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. these typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 v and mclk = 6.144 mhz. the conversion time is selected via the channel conversion time register. table 7. typical output rms noise in v vs. conver sion time and input range with chopping disabled input range rms noise (v) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v, +2.5 v 1.25 v, +1.25 v, 0.625 v, +0.625 v 127 0x7f 1358 737 675 2.4 1.5 92 0x5c 993 1007 950 3.0 1.8 35 0x23 399 2504 2500 4.5 2.7 16 0x10 201 4963 5400 6.9 4.1 12 0x0c 160 6257 7250 9.6 5.3 11 0x0b 149 6693 7900 11.4 6.9 3 0x03 66 15133 29000 200 90 table 8. typical effective resolution in bits vs. conv ersion time and input range with chopping disabled input range effective resolution (bits) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v +2.5 v 1.25 v +1.25 v 0.625 v +0.625 v 127 0x7f 1358 737 675 21.0 20.0 20.6 19.6 19.6 18.6 92 0x5c 993 1007 950 20.7 19.7 20.4 19.4 19.4 18.4 35 0x23 399 2504 2500 20.1 19.1 19.8 18.8 18.8 17.8 16 0x10 201 4963 5400 19.4 18.4 19.2 18.2 18.2 17.2 12 0x0c 160 6257 7250 18.9 17.9 18.8 17.8 17.8 16.8 11 0x0b 149 6693 7900 18.8 17.8 18.5 17.5 17.5 16.5 3 0x03 66 15133 29000 14.6 13.6 14.7 13.7 13.7 12.7 table 9. typical peak-to-peak resolution in bits vs. conversion time and input range with chopping disabled input range peak-to-peak resolution (bits) f conversion time register conversion time (s) output data rate (hz) C3 db freuency (hz) 2.5 v +2.5 v 1.25 v +1.25 v 0.625 v +0.625 v 127 0x7f 1358 737 675 18.2 17.2 17.8 16.8 16.8 15.8 92 0x5c 993 1007 950 17.8 16.8 17.6 16.6 16.6 15.6 35 0x23 399 2504 2500 17.2 16.2 17.0 16.0 16.0 15.0 16 0x10 201 4963 5400 16.6 15.6 16.4 15.4 15.4 14.4 12 0x0c 160 6257 7250 16.1 15.1 16.0 15.0 15.0 14.0 11 0x0b 149 6693 7900 16.0 15.0 15.7 14.7 14.7 13.7 3 0x03 66 15133 29000 11.7 10.7 12.0 11.0 11.0 10.0
ad7739 rev. 0 | page 12 of 32 pin configuration and fu nction descriptions top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7739 ain4 ain5 ain6 ain7 sync/p1 sclk mclkin mclkout cs aincom/p0 av dd reset ain3 ain2 ain1 ain0 refin(+) dgnd dv dd din dout refin(?) agnd rdy 03742-0-011 figure 11. pin configuration (24-lead tssop) dv dd serial interface control logic mux reference detect i/o port clock generator 24-bit 6 - ' adc buffer ad7739 calibration circuitry av dd sclk din dout cs rdy reset ain4 ain5 ain6 ain7 aincom/p0 ain0 ain1 ain2 ain3 refin(?) refin(+) sync/p1 dgnd dv dd mclkin mclkout agnd av dd 03742-0-012 figure 12. block diagram table 10. pin function descriptions pin no. mnemonic description 1 sclk serial clock. schmitt triggered lo gic input. an external serial clock is applied to this input to transfer serial data to or from the ad7739. 2 mclkin master clock signal for the adc. this can be pr ovided in the form of a crystalresonator or external clock. a crystalresonator can be tied across the mclkin and mclkot pins. alternatively, mclkin can be driven with a cmos compatible clock and mclkot can be left unconnected. 3 mclkot master clock signal for the adc. hen the master clock for the device is a crystal resonator, the crystalresonator is connect ed between mclkin and mclkot. if an external clock is applied to the mclkin, mc lkot provides an inverted clock signal or can be switched off to reduce the device power consumption. mclkot can drive one cmos load. 4 cs chip select. active low schmitt triggered logi c input with an internal pull-up resistor. ith this input hardwired low, the ad7739 can operate in its 3-wire interface mode using sclk, din, and dot. cs can be used to select the device in systems with more than one device on the serial bus. it can also be us ed as an 8-bit frame synchronization signal. 5 reset schmitt triggered logic input. active low inpu t that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. effectively, everything on the part exce pt the clock oscillator is reset when the reset pin is exercised. 6 av dd analog positive supply voltage, 5 v to and nominal. 7 aincomp0 analog inputs common terminaldigital output. the function of this pin is determined by the p0 dir bit in the io port register; the digital value can be written as the p0 bit in the io port register. the digital voltage is referenced to analog supplies. hen configured as an input (p0 dir bit set to 1) , the single-ended analog inputs 0 to 7 (ain0Cain7) can be referenced to this pins voltage level.
ad7739 rev. 0 | page 13 of 32 pin no. mnemonic description 8 sync /p1 sync /digital input/digital output. the pin dire ction is determined by the p1 dir bit; the digital value can be read/written as the p1 bit in the i/o port register. when the sync bit in the i/o port register is set to 1, then the sync /p1 pin can be used to synchronize the ad7739 modulator and digital filter with other devices in the system. the digital voltage is referenced to the analog supplies. when configured as an input, the pin should be tied high or low. 9?16 ain0?ain7 analog inputs. 17 refin(+) positive terminal of the differential referenc e input. refin(+) voltage potential can lie anywhere between av dd and agnd. in normal circuit configuration, this pin should be connected to a 2.5 v reference voltage. 18 refin(?) negative terminal of the differential referenc e input. refin(?) voltage potential can lie anywhere between av dd and agnd. in normal circuit configuration, this pin should be connected to a 0 v reference voltage. 19 agnd ground reference point for analog circuitry. 20 rdy logic output. used as a sta tus output in both conversion mo de and calibration mode. in conversion mode, a falling edge on this outp ut indicates that either any channel or all channels have unread data available, accordin g to the rdyfn bit in the i/o port register. in calibration mode, a falling edge on this output indicates that calibration is complete (see the digital interface description section for details). 21 dout serial data output. serial data is read from the output shif t register on the part. this output shift register can contain informat ion from any ad7739 register, depending on the address bits of the communications register. 22 din serial data input (schmitt trigge red). serial data is written to the input shift register on the part. data from this input shift regi ster is transferred to any ad7739 register, depending on the address bits of the communications register. 23 dv dd digital supply voltage, 3 v or 5 v nominal. 24 dgnd ground reference point for digital circuitry.
ad7739 rev. 0 | page 14 of 32 register descriptions table 11. register summary register addr dir bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) default value 0 r 6-bit register address communications 0x00 p0 p1 p0 dir p1 dir rdfn redpr 0 snc io port 0x01 r p0 pin p1 pin 1 1 0 0 0 0 chip revision code chip eneric code revision 0x02 r x x x x 1 0 0 1 24-bit manufacturing test register test 0x03 r rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 adc status 0x04 r 0 0 0 0 0 0 0 0 16-bit checksum register checksum 0x05 r 24-bit adc ero-scale calibration register adc ero-scale calibration 0x06 r 0x80 0000 24-bit adc full-scale register adc full-scale calibration 0x07 r 0x80 0000 16-24-bit data registers channel data 1 0x08C0x0f r 0x8000 24-bit channel ero-scale calibration registers channel ero-scale cal. 1 0x10C0x17 r 0x80 0000 24-bit channel full-scale calibration registers channel full-scale cal. 1 0x18C0x1f r 0x20 0000 ch2 ch1 ch0 0p0 rdp1 noref sin ovr channel status 1 0x20C0x27 r channel number 0 0 0 0 0 bfoff com1 com0 stat opt enable rn2 rn1 rn0 channel setup 1 0x28C0x2f r 0 0 0 0 0 0 0 0 chop f (7-bit filter ord) channel conversion time 1 0x30C0x37 r 1 0x11 md2 md1 md0 clkdis dmp cont rd 2416 bit clamp mode 2 0x38C0x3f r 0 0 0 0 0 0 0 0 1 the three lsbs of the register address, i.e., bit 2, bit 1, and bit 0 in the communications register, specify the channel numbe r of the register being accessed. 2 the ad7739 has only one mode register, although the mode register can be accessed in one of eig ht address locations. the addres s used to write the mode register specifies the adc channel on which the mode will be applied. only address 0x38 must be used for reading from the mode register. table 12. operational mode summary md2 md1 md0 mode 0 0 0 idle 0 0 1 continuous conversion 0 1 0 single conversion 0 1 1 power-down (standby) 1 0 0 adc ero-scale self-calibration 1 0 1 adc full-scale self-calibration (for 2.5 v) 1 1 0 channel ero-scale system calibration 1 1 1 channel full-scale system calibration table 13. input range summary rn2 rn1 rn0 nominal input voltage range 1 0 0 2.5 v 1 0 1 +2.5 v 0 0 0 1.25 v 0 0 1 +1.25 v 0 1 0 0.625 v 0 1 1 +0.625 v
ad7739 rev. 0 | page 15 of 32 register access the ad7739 is configurable through a series of registers. some of them configure and control general ad7739 features, while others are specific to each channel. the register data widths vary from 8 bits to 24 bits. all registers are accessed through the communications register, i.e., any communication to the ad7739 must start with a write to the communications register specifying which register will be subsequently read or written. communications register 8 bits, write-only register, address 0x00 all communications to the part must start ith a rite operation to the communications register he data ritten to the communications register determines hether the subseuent operation ill be a read or rite and to hich register this operation ill be directed he digital interface defaults to expect a rite operation to the communications register after poer-on, after reset, or after the subseuent read or rite operation to the selected register is complete if the interface seuence is lost, the part can be reset by riting at least 32 serial clock cycles ith din high and cs lo note that all of the parts, including the modulator, filter, interface, and all registers are reset in this case remember to keep din lo hile reading 32 bits or more either in continuous read mode or ith the dum bit and 24/16 bit in the mode register set bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic 0 r/w 6-bit register address bit mnemonic description 7 0 his bit must be 0 for proper operation 6 r/w a 0 in this bit indicates that the next opera tion ill be a rite to a specified register a 1 in this bit indicates that the next operati on ill be a read from a specified register 5C0 address hese bits specify to hich register the read or rite operation ill be directed for channel specific registers, the three sbs, ie, bit2, bit 1, and bit 0, specify the channel number when the subseuent operation rites to the mode register, the three sbs specify the channel selected for th e operation determined by the mode register value he analog inputs configuration depe nds on the com1 and com0 bits in the channel setup register bit 2 bit 1 bit 0 channel single input differential input 0 0 0 0 ain0Caincom ain0Cain1 0 0 1 1 ain1Caincom ain2Cain3 0 1 0 2 ain2Caincom ain4Cain5 0 1 1 3 ain3Caincom ain6Cain7 1 0 0 4 ain4Caincom ain0Cain1 1 0 1 5 ain5Caincom ain2Cain3 1 1 0 6 ain6Caincom ain4Cain5 1 1 1 7 ain7Caincom ain6Cain7
ad7739 rev. 0 | page 16 of 32 i/o port register 8 bits, read/write register, address 0x01, default value 0x30 + digital input value 0x40 he bits in this register are used to configure and access the digital i/o port on the ad7739 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic 0 1 0 dir 1 dir rdfn rdwr 0 snc default 0 in 1 in 1 1 0 0 0 0 bit mnemonic description 7, 6 0, 1 when the 0 and 1 pins are configured as outputs, th e 0 and 1 bits determine the pins output level when the 0 and 1 pins are configured as inputs, the 0 an d 1 bits reflect the current input level on the pins 5, 4 0 dir, 1 dir hese bits determine hether the 0 and 1 pins are co nfigured as inputs or o utputs when set to 1, the corresponding pin ill be an input hen reset to 0, the corresponding pin ill be an output 3 rdfn his bit is used to control the function of the rd pin on the ad7739 when this bit is reset to 0, the rd pin goes lo hen any channel has unread data when this bit is set to 1, the rd pin ill go lo only if all enabled channels have unread data 2 rdwr reduced oer if this bit is set to 1, the ad7739 orks in the reduced poer mode he maximum mc freuency is limited to 4 m in the reduced poer mode 1 0 his bit must be 0 for proper operation 0 snc his bit enables the snc pin function by default, this bit is 0 and snc /1 can be used as a digital i/o pin when the snc bit is set to 1, the snc pin can be used to synchronie the ad7739 modulator and digital filter ith other devices in the system rvision risr 8 bits, read-only register, address 0x02, default value 0x09 + chip revision 0x10 bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic chip revision code chip eneric code default x x x x 1 0 0 1 bit mnemonic description 7C4 chip revision code 4-bit factory chip revision code 3C0 chip eneric code on the ad7739, these bits ill read back as 0x09 s risr 24 bits, read/write register, address 0x03 his register is used for testing the part in the manufacturing process he user must not change the default configuration of this register
ad7739 rev. 0 | page 17 of 32 adc status register 8 bits, read-only register, address 0x04, default value 0x00 in conversion modes, the register bits reflect the individual channel status when a conversion is complete, the corresponding channel data register is updated and the corresponding rd bit is set to 1 when the channel data register is read, the corresponding b it is reset to 0 he bit is reset to 0 also hen no read operation has ta ken place and the result of the next conversion is being updated to the channel data register writing to the mode register resets all the bits to 0 in calibration modes, all the register bits are reset to 0 hile a calibration is in progress all the register bits are set to 1 hen the calibration is complete he rd pin output is related to the content of the adc status register as defined by the rdfn bit in the i/o port register he rd0 bit corresponds to channel 0, the rd1 bit corresponds to channel 1, and so on bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 default 0 0 0 0 0 0 0 0 ccsum risr 16 bits, read/write register, address 0x05 his register is described in the using the ad7732/ad7734/ ad7738/ad7739 checksum register application note analogcom/uploadedfiles/applicationnotes/71751876 an6260pdf adc ro-sca caibraion risr 24 bits, read/write register, address 0x06, default value 0x80 0000 his register holds the adc ero-scale calibration coefficient he value in this register is us ed in conunction ith the value in the adc full-scale calibration register and the corresponding channel ero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels he value in this register is updated automatically folloing the execution of an adc ero-scale self-calibration writing this register is possible in the idle mode only see the calibration section for details adc fu-sca caibraion risr 24 bits, read/write register, address 0x07, default value 0x80 0000 his register holds the adc full-scale calibration coefficient he value in this register is us ed in conunction ith the value in the adc ero-scale and the corresponding channel ero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels he value in this register is updated automatically folloing the execution of an adc full-scale self-calibration writing this register is possible in the idle mode only he adc full-scale self-calibration should be used only on +25 v and 25 v input voltage ranges see the calibration section for details cann daa risrs 16 bit/24 bit, read-only registers, address 0x08C0x0f, default width 16 bits, default value 0x8000 hese registers contain the most up-to-date conversion results corresponding to each analog input channel he 16-bit or 24-bit data idth can be configured by setting the 24/16 bit in the mode register he relevant rd bit in the channel status register goes high hen the result is updated he rd bit ill return lo once the data register reading has begun he rd pin can be configured to indicate hen any channel has unread data or aits until all enabled channels have unread data if any channel data register read operation is in progress hen a ne result is updated, no update of the data register ill occur his avoids having corrupted data reading the status registers can be associated ith reading the data registers in the dump mode reading the status registers is alays associated ith reading the data registers in the continuous read mode see the digital interface description section for details
ad7739 rev. 0 | page 18 of 32 channel zero-scale calibration registers 24 bits, read/write registers, address 0x10C0x17, default value 0x80 0000 hese registers hold the particular channel ero-scale calibration coefficients he value in these registers is used in conunction ith the value in the corresponding channel full- scale calibration register, the adc ero-scale calibration register, and the adc full-scale calibration register to digitally scale the particular channel conversion results he value in this register is updated automatically folloing the execution of a channel ero-scale system calibration he format of the channel ero-scale calibration register is a sign bit and a 22-bit unsigned value writing this register is possible in the idle mode only see the calibration section for details cann fu-sca caibraion risrs 24 bits, read/write registers, address 0x18C0x1f, default value 0x20 0000 hese registers hold the particular channel full-scale calibration coefficients he value in these registers is used in conunction ith the value in the corresponding channel ero-scale calibration register, the adc ero-scale calibration register, and the adc full-scale calibration register to digitally scale the particular channel conversion results he value in this register is updated automatically folloing the execution of a channel full-scale system calibration writing this register is possible in the idle mode only see the calibration section for details cann saus risrs 8 bits, read-only registers, address 0x20C0x27, default value 0x20 channel number hese registers contain individual channel status information a nd some general ad7739 status information reading the status re gisters can be associated ith reading the data registers in the dump mode reading the status registers is alays associated ith read ing the data registers in the continuous read mode see the digital interface description section for details bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic c2 c1 c0 0/0 rd/1 norf sin ovr default channel number 0 0 0 0 0 bit mnemonic description 7C5 c2Cc0 hese bits reflect the channel number his can be used for current channel identification and easier operation of the dump mode and continuous read mode 4 0/0 when the status option bit of the corresp onding channel setup register is rese t to 0, this bit is read as a 0 when the status option bit is set to 1, this bit reflects the state of the 0 pin, hether it is configured as an input or an output 3 rd/1 when the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel rd bit in the adc status register when the status option bit is set to 1, this bit reflects the state of the 1 pin, hether it is co nfigured as an input or an output 2 norf his bit indicates the reference input status if the voltage beteen the rfi n+ and rfinC pins is less than norf, the trigger voltage, and a conversion is executed, then the norf bit goes to 1 1 sin his bit reflects the voltage polarity at the analog input it ill be 0 for a positive voltage and 1 for a negative voltage 0 ovr his bit reflects either the overrange or the underrang e on the analog input he bit is set to 1 hen the analog input voltage goes over or under the nominal voltage range see th e analog inputs xtended voltage range section
ad7739 rev. 0 | page 19 of 32 channel setup registers 8 bits, read/write registers, address 0x28C0x2f, default value 0x00 hese registers are used to configure the selected channel, to configure its input voltage range, and to set up the correspondi ng channel status register bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic bufoff com1 com0 stat o nab rn2 rn1 rn0 default 0 0 0 0 0 0 0 0 bit mnemonic description 7 bufoff buffer off if reset to 0, th en the internal buffer is enabled operation only ith the internal buffer enabled is recommended 6C5 com1, com0 analog inputs configuration com1 com0 com1 com0 channel 0 0 1 1 0 ain0Caincom ain0Cain1 1 ain1Caincom ain2Cain3 2 ain2Caincom ain4Cain5 3 ain3Caincom ain6Cain7 4 ain4Caincom ain0Cain1 5 ain5Caincom ain2Cain3 6 ain6Caincom ain4Cain5 7 ain7Caincom ain6Cain7 4 stat o status option when this bit is set to 1, the 0 and 1 bits in the channel st atus register ill reflect the state of the 0 and 1 pins when this bit is reset to 0, the rd bit in the channel status register ill reflect the channel corresponding to the rd bit in the adc status register 3 nab channel nable set this bi t to 1 to enable the channel in the continuous conversi on mode a single conversion ill take place regardless of this bits value 2C0 rn2Crn0 his is the channel input voltage range rn2 rn1 rn0 nominal input voltage range 1 0 0 25 v 1 0 1 +25 v 0 0 0 125 v 0 0 1 +125 v 0 1 0 0625 v 0 1 1 +0625 v
ad7739 rev. 0 | page 20 of 32 channel conversion time registers 8 bits, read/write registers, address 0x30C0x37h, default value 0x91 he conversion time registers enable or disable chopping and configure the digital filter for a particular channel his regist er value affects the conversion time, freuency response, and noise performance of the adc bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic co fw 7-bit filter word default 1 0x11 bit mnemonic description 7 co chopping nable bit set to 1 to a pply chopping mode for a particular channel 6C0 fw co 1, single conversion or continuous conversion ith one channel enabled conversion ime s fw 128 + 262/mc freuency m, the fw range is 2 to 127 co 1, continuous conversion ith to or more channels enabled conversion ime s fw 128 + 263/mc freuency m, the fw range is 2 to 127 co 0, single conversion or continuous conversion ith one channel enabled conversion ime s fw 64 + 213/mc freuency m, the fw range is 3 to 127 co 0, continuous conversion ith to or more channels enabled conversion ime s fw 64 + 214/mc freuency m, the fw range is 3 to 127 mod risr 8 bits, read/write register, address 0x38C0x3f, default value 0x00 he mode register configures the part and determines its operating mode writing to the mode register clears the adc status reg ister, sets the rd pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits he ad7739 contains only one mode register he to sbs of the address are used for riting to the mode register to specify th e channel selected for the operation determined by the md2 to md0 bits on ly the address 0x38 must be used for reading from the mode regi ster bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mnemonic md2 md1 md0 cdis dum cont rd 24/16 bi cam default 0 0 0 0 0 0 0 0 bit mnemonic description 7C5 md2Cmd0 mode bits hese three bits determine the ad7739 operation mode writing a ne value to the mode bits ill exit the part from the mode in hich it has been operating and place it in the nely reuested mode immediately he function of the mode bits is described in more detail belo md2 md1 md0 mode address used for mode register write specifies 0 0 0 idle 0 0 1 continuous conversion fi rst channel to start converting 0 1 0 single conversion channel to convert 0 1 1 oer-don standby 1 0 0 adc ero-scale self-calibration conversion ime for calibration 1 0 1 adc full-scale self-calibration for 25 v conversion ime for calibration 1 1 0 channel ero-scale system calibration channel to calibrate 1 1 1 channel full-scale system calibration channel to calibrate
ad7739 rev. 0 | page 21 of 32 bit mnemonic description 4 clkdis master clock output disable. when this bit is set to 1, the master clock is disabled from appearing at the mclkout pin and the mclkout pin is in a high impedan ce state. this allows turning off the mclkout as a power saving feature. when using an external clock on mclkin, the ad7739 continues to have internal clocks and will convert normally regardless of the clkdis bit state. when using a crystal oscillator or ceramic resonator across the mclkin and mclkout pins , the ad7739 clock is stopped and no conversions can take place when the clkdis bit is active. the ad7739 digital interf ace can still be accessed using the sclk pin. 3 dump dump mode. when this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. when the dump bit is set to 1, th e channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communications register. the contin uous read mode will always be dump mode reading the channel status and channel data registers, regardless of the dump bit value (see the digital interface description section for details). 2 cont rd when this bit is set to 1, the ad7739 will operate in the continuous read mode (see the digital interface description section for details). 1 24/16 bit channel data register data width selection bit. when se t to 1, the channel data registers will be 24 bits wide. when set to 0, the channel data registers will be 16 bits wide. 0 clamp this bit determines the channel data register?s value wh en the analog input voltage is outside the nominal input voltage range. when the clamp bit is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. when the clamp bit is reset to 0, the data registers reflect the analog inp ut voltage even outside the nominal voltage range (see the analog input?s extended voltage range section). md2 md1 md0 operating mode description 0 0 0 idle the default mode after power-on or reset. the ad 7739 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 continuous conversion the ad7739 performs a conversion on the specified channel. after the conversion is complete, the relevant channel data register and channel status register are updated, the relevant rdy bit in the adc status register is set, and the ad7739 continue s converting on the next enabled channel. the part will cycle through all enabled channels until it is put into another mode or reset. the cycle period will be the sum of all enabled channels? conversion times, set by the corresponding channel conversion time registers. 0 1 0 single conversion the ad7739 performs a conversion on the specified channel. after the conversion is complete, the relevant channel data register and channel status register are updated, the relevant rdy bit in the adc status register is set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7739 returns to idle mode. requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 power-down (standby) the adc and the analog front end (internal bu ffer) go into the power-down mode. the ad7739 digital interface can still be accessed. the clkdis bit works separately, and the mclkout mode is not affected by the power-down (standby) mode. 1 0 0 adc zero-scale self-calibration a zero-scale self-calibration is performed on inte rnally shorted adc inputs. after the calibration is complete, the contents of the adc zero-scale calibrat ion register are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7739 returns to idle mode. 1 0 1 adc full-scale self-calibration a full-scale self-calibration is performed on an internally generated full-scale signal. after the calibration is complete, the conten ts of the adc full-scale calibration register are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are reset, and the ad7739 returns to idle mode. 1 1 0 channel zero- scale system calibration a zero-scale system calibration is performed on the selected channel. an external system zero-scale voltage should be provided at the ad7739 analog input and this vo ltage should remain stable for the duration of the calibration. after the calibratio n is complete, the contents of the corresponding channel zero-scale calibration register are updated, all rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are re set, and the ad7739 returns to idle mode. 1 1 1 channel full- scale system calibration a full-scale system calibration is performed on the selected channel. an external system full-scale voltage should be provided at the ad7739 analog input and this vo ltage should remain stable for the duration of the calibration. after the calibratio n is complete, the contents of the corresponding channel full-scale calibration register are updated, a ll rdy bits in the adc status register are set, the rdy pin goes low, the md2?md0 bits are re set, and the ad7739 returns to idle mode.
ad7739 rev. 0 | page 22 of 32 digital interface description hardware the ad7739 serial interface can be connected to the host device via the serial interface in several different ways. the cs pin can be used to select the ad7739 as one of several circuits connected to the host serial interface. when cs is high, the ad7739 ignores the sclk and din signals and the dout pin goes to the high impedance state. when the cs signal is not used, connect the cs pin to dgnd. the rdy pin can be polled for high-to-low transition or can drive the host device interrupt input to indicate that the ad7739 has finished the selected operation and/or new data from the ad7739 is available. the host system can also wait a designated time after a given command is written to the device before reading. alternatively, the ad7739 status can be polled. when the rdy pin is not used in the system, it should be left as an open circuit. (note that the rdy pin is always an active digital output, i.e., it never goes into a high impedance state.) the reset pin can be used to reset the ad7739. when not used, connect this pin to dv dd . the ad7739 interface can be reduced to just two wires connecting the din and dout pins to a single bidirectional data line. the second signal in this 2-wire configuration is the sclk signal. the host system should change the data line direction with reference to the ad7739 timing specification (see the bus relinquish time in table 2). the ad7739 cannot operate in the continuous read mode in 2-wire serial interface configuration. all the digital interface inputs are schmitt triggered; therefore, the ad7739 interface features higher noise immunity and can be easily isolated from the host system via optocouplers. figure 13, figure 14, and figure 15 outline some of the possible host device interfaces: spi without using the cs signal (figure 13), a dsp interface (figure 14), and a 2-wire configuration (figure 15). sclk din dout cs rdy reset dgnd dv dd dv dd ad7739 sck mosi miso int 68hc11 ss 03742-0-013 figure 13. ad7739 to host device interface, spi sclk din dout cs rdy reset dv dd ad7739 sclk dt dr int tfs rfs adsp-2105 03742-0-001 figure 14. ad7739 to host device interface, dsp sclk din dout cs reset dgnd dv dd ad7739 p3.1/txd p3.0/rxd 8xc51 03742-0-015 figure 15. ad7739 to host device interface, 2-wire configuration din sclk cs dout write communications register read adc status register 03742-0-016 figure 16. serial interface signals?registers access
ad7739 rev. 0 | page 23 of 32 reset the ad7739 can be reset by the reset pin or by writing a reset sequence to the ad7739 serial interface. the reset sequence is n 0 + 32 1, which could be the data sequence 0x00 + 0xff + 0xff + 0xff + 0xff in a byte-oriented interface. the ad7739 also features a power-on reset with a trip point of 2 v and goes to the defined default state after power-on. it is the system designer?s responsibility to prevent an unwanted write operation to the ad7739. the unwanted write operation could happen when a spurious clock appears on the sclk while the cs pin is low. note that if the ad7739 interface signals are floating or undefined at system power-on, the part can be inadvertently configured into an unknown state. this could be easily overcome by initiating either a hardware reset event or a 32 ones reset sequence as the first step in the system configuration. access the ad7739 registers all communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register. in a simultaneous read-write interface (such as spi), write 0 to the ad7739 while reading data. figure 16 shows the ad7739 interface read sequence for the adc status register. single conversion and reading data when the mode register is being written, the adc status byte is cleared and the rdy pin goes high, regardless of its previous state. when the single conversion command is written to the mode register, the adc starts the conversion on the channel selected by the address of the mode register. after the conversion is completed, the data register is updated, the mode register is changed to idle mode, the relevant rdy bit is set, and the rdy pin goes low. the rdy bit is reset and the rdy pin returns high when the relevant channel data register is being read. figure 17 shows the digital interface signals executing a single conversion on channel 0, waiting for the rdy pin to go low, and reading the channel 0 data register. dump mode when the dump bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or the data register has been addressed through the communications register. the din pin should not be high while reading 24-bit data in dump mode; otherwise, the ad7739 will be reset. figure 18 shows the digital interface signals executing a single conversion on channel 0, waiting for the rdy pin to go low, and reading the channel 0 status register and data register in the dump mode. din sclk cs dout write communications register write mode register rdy conversion time read data register 0x38 0x40 0x48 (0x00) (0x00) data data write communications register 03742-0-017 figure 17. serial interface signals?single conversion command and 16-bit data reading din sclk cs dout write communications register write mode register rdy conversion time read data register read channel status 0x38 0x48 0x48 write communications register (0x00) (0x00) (0x00) status data data 03742-0-018 figure 18. serial interface signals?single conversion command, 16-bit data reading, dump mode
ad7739 rev. 0 | page 24 of 32 continuous conversion mode when the mode register is being written, the adc status byte is cleared and the rdy pin goes high, regardless of its previous state. when the continuous conversion command is written to the mode register, the adc starts conversion on the channel selected by the address of the mode register. after the conversion is complete, the relevant channel data register and channel status register are updated, the relevant rdy bit in the adc status register is set, and the ad7739 continues converting on the next enabled channel. the part will cycle through all enabled channels until put into another mode or reset. the cycle period will be the sum of all enabled channels? conversion times, set by the corresponding channel conversion time registers. the rdy bit is reset when the relevant channel data register is being read. the behavior of the rdy pin depends on the rdyfn bit in the i/o port register. when the rdyfn bit is 0, the rdy pin goes low when any channel has unread data. when the rdyfn bit is set to 1, the rdy pin will go low only if all enabled channels have unread data. if an adc conversion result has not been read before a new adc conversion is completed, the new result will overwrite the previous one. the relevant rdy bit goes low and the rdy pin goes high for at least 163 mclk cycles (~26.5 s), indicating when the data register is updated, and the previous conversion data is lost. if the data register is being read as an adc conversion completes, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data is lost. figure 19 shows the digital interface signal?s sequence for the continuous conversion mode with channels 0 and 1 enabled and the rdyfn bit set to 0. the rdy pin goes low and the data register is read after each conversion. figure 20 shows a similar sequence but with the rdyfn bit set to 1. the rdy pin goes low and all data registers are read after all conversions are completed. figure 21 shows the rdy pin when no data is read from the ad7739. serial interface start continuous conversion rdy ch0 conversion read data ch1 ch1 conversion ch0 conversion read data ch0 ch1 conversion read data ch0 ch0 conversion read data ch1 03742-0-019 figure 19. continuous conversion, ch0 and ch1, rdyfn = 0 serial interface start continuous conversion rdy ch0 conversion read data ch1 ch1 conversion ch0 conversion read data ch0 ch1 conversion read data ch0 ch0 conversion read data ch1 03742-0-020 figure 20. continuous conversion, ch0 and ch1, rdyfn = 1 serial interface start continuous conversion rdy ch0 conversion ch1 conversion ch0 conversion ch1 conversion ch0 conversion 03742-0-021 figure 21. continuous conversion, ch0 and ch1, no data read
ad7739 rev. 0 | page 25 of 32 continuous read (continuous conversion) mode when the cont rd bit in the mode register is set, the first write of 0x48 to the communications register starts the continuous read mode. as shown in figure 22, subsequent accesses to the part sequentially read the channel status and data registers of the last completed conversion without any further configuration of the communications register being required. note that the continuous conversion bit in the mode register should be set when entering the continuous read mode. note that the continuous read mode is a dump mode reading of the channel status and data registers regardless of the dump bit value. use the channel bits in the channel status register to check/recognize which channel data is actually being shifted out. note that the last completed conversion result is being read. therefore, the rdyfn bit in the i/o port register should be 0, and reading the result should always start before the next conversion is completed. the ad7739 will stay in continuous read mode as long as the din pin is low while the cs pin is low; therefore, write 0 to the ad7739 while reading in continuous read mode. to exit continuous read mode, take the din pin high for at least 100 ns after a read is complete. (write 0x80 to the ad7739 to exit continuous reading.) taking the din pin high does not change the cont rd bit in the mode register. therefore, the next write of 0x48 starts the continuous read mode again. to completely stop the continuous read mode, write to the mode register to clear the cont rd bit. din 0x48 (0x00) data (0x00) data (0x00) status read ch0 data read ch0 status 0x48 write comm. register sclk cs dout write comm. register write mode register rdy 0x38 (0x00) data (0x00) data (0x00) status read ch1 data read ch1 status conversion on ch0 complete conversion on ch1 complete 03742-0-022 figure 22. continuous conversion, ch0 and ch1, continuous read
ad7739 rev. 0 | page 26 of 32 circuit description the ad7739 is a high precision analog-to-digital converter that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and plc systems. it contains a multiplexer, an input buffer, a sigma-delta (or charge balancing) adc, a digital filter, a clock oscillator, a digital i/o port, and a serial communications interface. analog inputs the ad7739 has nine analog input pins connected to the adc through the internal multiplexer. the analog front end can be configured as eight single-ended inputs or four differential inputs or any combination of these (via the channel setup registers). the ad7739 contains a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma-delta modulator. with the internal buffer enabled, the analog inputs feature high input impedance. if chopping is enabled or when switching between channels, there is a dynamic current on analog inputs charging the internal capacitance of the multiplexer and input buffer. the capacitance is approximately 10 pf. at the start of each conversion, there is a delay to allow the capacitance to be charged (see the multiplexer, conversion, and data output timing section). if the analog inputs resistive source impedance does not exceed 50 k, the internal capacitance is charged fast enough and the ad7739 performance is not affected at the 16-bit level. an external rc filter connected to the analog inputs would average the multiplexer channel-to-channel switching dynamic currents to a dc current leading to a dc voltage drop across the external input resistance. to avoid additional gain errors, offset errors, and channel-to-channel crosstalk due to this effect, low resistor values should be used in the low-pass rc filter for the ad7739. the recommended low-pass rc filter for the analog inputs is 100 and 100 nf. the average (dc) current, charging the capacitance on the multiplexer output, is related to the equation: i c mux is the capacitance on the multiplexer output, approximately 10 pf , v mux is the voltage difference on the multiplexer output beteen to subseuent conversions, hich can be up to 5 v, and f s is the channel sampling freuency, hich relates to the sum of conversion times on all subseuently sampled channels sima-da adc he ad7739 core consists of a charge balancing sigma-delta modulator and a digital filter he architecture is optimied for fast, fully settled conversion his allos for fast channel-to- channel sitching hile maintaining inherently excellent linearity, high resolution, and lo noise coin with chopping enabled, the multiplexer repeatedly reverses the adc inputs very output data result is then calculated as an average of to conversions, the first ith the positive and the second ith the negative offset term included his effectively removes any offset error of the input buffer and sigma-delta modulator figure 23 shos the channel signal chain ith chopping enabled muixr + diia fir 6 - moduaor buffr scain arimic caibraions co co co f mc /2 diia inrfac ouu daa a scd daa ra a in+ a in 03742-0-023 figure 23 channel signal chain diagram ith chopping nabled
ad7739 rev. 0 | page 27 of 32 multiplexer, conversion, and data output timing the specified conversion time includes one or two settling and sampling periods and a scaling time. with chopping enabled (figure 24), a conversion cycle starts with a settling time of 43 mclk cycles or 44 mclk cycles (~7 s with a 6.144 mhz mclk) to allow the circuits following the multiplexer to settle. the sigma-delta modulator then samples the analog signals and the digital filter processes the digital data stream. the sampling time depends on fw, i.e., on the channel conversion time register contents. after another settling of 42 mclk cycles (~6.8 s), the sampling time is repeated with a reversed (chopped) analog input signal. then, during the scaling time of 163 mclk cycles (~26.5 s), the two results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register. with chopping disabled (figure 25), only one sampling time is preceded by a settling time of 43 mclk or 44 mclk cycles and followed by a scaling time of 163 mclk cycles. the rdy pin goes high during the scaling time, regardless of its previous state. the relevant rdy bit is set in the adc status register and in the channel status register, and the rdy pin goes low when the channel data register is updated and the channel conversion cycle is finished. if in continuous conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel. note that every channel can be configured independently for conversion time and chopping mode. the overall cycle and effective per channel data rates depend on all enabled channel settings. ? channel 1 scaling time sampling time + channel 1 sampling time settling time multiplexer ? channel 0 rdy settling time conversion time 03742-0-024 figure 24. multiplexer and conversion timing?continuous conversion on several channels with chopping enabled scaling time channel 1 sampling time multiplexer channel 0 rdy settling time conversion time 03742-0-025 figure 25. multiplexer and conversion timing?continuous conversion on several channels with chopping disabled
ad7739 preliminary technical data rev. 0 | page 28 of 32 frequency response the sigma-delta modulator runs at ? the mclk frequency, which is effectively the sampling frequency. therefore, the modulator nyquist frequency is ? of the mclk. if chopping is enabled, the input signal is resampled by chopping. therefore, the overall frequency response features notches close to the frequency of 1/channel conversion time. the typical adc frequency response plots are given in figure 26 and figure 27. the plots are normalized to 1/channel conversion time. note that these figures apply to each channel separately and are based on individual channel conversion time. the signal is effectively resampled once more in the multiplexer by switching between enabled analog inputs. normalized input frequency (input frequency u conversion time) gain (db) ?120 ?100 ?80 ?60 ?40 ?20 0 010 1 100 chop = 1 03742-0-026 figure 26. typical adc frequency response, chopping enabled normalized input frequency (input frequency u conversion time) gain (db) ?120 ?100 ?80 ?60 ?40 ?20 0 010 1 100 chop = 0 03742-0-027 figure 27. typical adc frequency response, chopping disabled
ad7739 rev. 0 | page 29 of 32 analog input?s extended voltage range the ad7739 output data code span corresponds to the nominal input voltage range. the adc is functional outside the nominal input voltage range, but the performance might degrade. the sigma-delta modulator was designed to fully cover 16% analog input overrange; outside this range, the performance might degrade more rapidly. when the clamp bit in the mode register is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. as shown in table 14 and table 15, when clamp = 0, the data reflects the analog input voltage outside the nominal voltage range. in this case, the sign and ovr bits in the channel status register should be considered along with the data register value to decode the actual conversion result. note that the ovr bit in the channel status register is generated digitally from the conversion result and indicates the sigma- delta modulator (nominal) overrange. the ovr bit does not indicate exceeding the ain pin?s absolute voltage limits. table 14. extended input voltage range, nominal voltage range 1.25 v, 16 bits, clamp = 0 input (v) data (hex) sin ovr +1.45000 0x147b 0 1 +1.25008 0x0001 0 1 +1.25004 0x0000 0 1 +1.25000 0xffff 0 0 +0.00004 0x8001 0 0 0.00000 0x8000 0 0 C0.00004 0x7fff 1 0 C1.25000 0x0000 1 0 C1.25004 0xffff 1 1 C1.25008 0xfffe 1 1 C1.45000 0xeb85 1 1 table 15. extended input voltage range, nominal voltage range +1.25 v, 16 bits, clamp = 0 input (v) data (hex) sin ovr +1.45000 0x28f5 0 1 +1.25004 0x0001 0 1 +1.25002 0x0000 0 1 +1.25000 0xffff 0 0 +0.00002 0x0001 0 0 +0.00000 0x0000 0 0 C0.00002 0x0000 1 1 voltae reference inpts the ad7739 has a differential reference input, ref in(+) and ref in(C). the common-mode range for these inputs is from and to av dd . the nominal differential reference voltage for specified operation is 2.5 v. both reference inputs feature dynamic load. therefore, the reference inputs should be connected to a low impedance reference voltage source. external resistancecapacitance combinations may result in gain errors on the part. the output noise performance outlined in table 4 through table 9 is for an analog input of 0 v and is unaffected by noise on the reference. obtaining the same noise performance as shown in the noise tables over the full input range reuires a low noise reference source for the ad7739. if the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the ad7739. recommended reference voltage sources for the ad7739 include the adr421, ad780, ref43, and ref192. reference detect the ad7739 includes on-chip circuitry to detect if the part has a valid reference for conversions. if the voltage between the refin(+) and refin(C) pins goes below the noref trigger voltage (0.5 v typ.) and the ad7739 is performing a conversion, the noref bit in the channel status register is set. io port the ad7739 p0 pin can be used as a general-purpose digital output or as a common analog input. the p1 pin ( snc p1) can be used as a general-purpose digital io pin or to synchronize the ad7739 with other devices in the system. hen the snc bit in the io port register is set and the snc pin is low, the ad7739 does not process any conversion. if it is put into single conversion mode, continuous conversion mode, or any calibration mode, the ad7739 waits until the snc pin goes high and then starts operation. this allows conversion to start from a known point in time, i.e., the rising edge of the snc pin. hen configured as input, the snc pin should be tied high or low. the digital p0 and p1 voltage is referenced to the analog supplies.
ad7739 rev. 0 | page 30 of 32 calibration the ad7739 provides zero-scale self-calibration, and zero- and full-scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise. after each conversion, the adc conversion result is scaled using the adc calibration registers and the relevant channel calibration registers before being written to the data register. for unipolar ranges: data = ((adc result ? r adc zs cal. reg.) adc fs reg./(0x20 0000) ? r ch. zs cal. reg.) ch. fs cal. reg./(0x20 0000) for bipolar ranges: data = ((adc result ? r adc zs cal. reg.) adc fs reg./(0x40 0000) + (0x80 0000) ? r ch. zs cal. reg.) ch. fs cal. reg./(0x20 0000) where the adc result is in the range of 0 to 0xff ffff. r = 1 for input ranges +1.25 v, 1.25 v, +2.5 v, and 2.5 v r = 2 for input ranges +0.625 v, and 0.625 v note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. to start any calibration, write the relevant mode bits to the ad7739 mode register. after the calibration is complete, the contents of the corresponding calibration registers are updated, all rdy bits in the adc status register are set, the sync pin goes low, and the ad7739 reverts to idle mode. the calibration duration is the same as the conversion time configured on the selected channel. a longer conversion time gives less noise and yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration. adc zero-scale self-calibration he adc ero-scale self-calibration can reuce the adc offset error in the choin isable moe f reeate after a temerature chane it can also reuce the offset rift error in the choin isable moe he ero-scale self-calibration is erforme on internally shorte adc inuts he neatie analo inut terminal on the selecte channel is use to set the adc ero-scale calibration common moe herefore either the neatie terminal of the selecte ifferential air or the ac on the sinle-ene channel confiuration shoul be rien to a roer common- moe oltae t is recommene that the adc ero-scale calibration reister be uate only as art of an adc ero-scale self-calibration adc full-scale self-calibration he adc full-scale self-calibration can reuce the adc full- scale error for the an inut rane f reeate after a temerature chane it can also reuce the full-scale rift he adc full-scale self-calibration is erforme ith a inut oltae rane on internally enerate full-scale oltae f rearless of the inut oltae rane set in the channel setu reister full-scale errors in the an ranes are not calibrate as this oul reuire an accurate lo oltae source other than the reference f the or ranes are use on any channel the adc full-scale self-calibration is not recommene a system full-scale calibration shoul be erforme if accurate ains nee to be achiee on these ranes t is recommene that the adc full-scale calibration reister be uate only as art of an adc full-scale self-calibration for the an inut rane per channel system calibration he er channel system calibration can reuce the system offset error an the system ain error f reeate after a temerature chane it can also reuce the system offset an ain rifts f the er channel system calibrations are use these shoul be initiate in the folloin orer a channel ero-scale system calibration folloe by a channel full-scale system calibration he system calibration is affecte by the adc ero-scale an full-scale calibration reisters herefore if both self-calibration an system calibration are use in the system an adc self- calibration shoul be erforme first folloe by a system calibration cycle he oltae rane in the channel setu reister shoul be set before eecutin the channel system calibration hile eecutin a system calibration the fully settle system ero-scale oltae sinal or system full-scale oltae sinal must be connecte to the selecte channel analo inuts he er channel calibration reisters can be rea store or moifie an ritten bac to the ad ote that hen ritin the calibration reisters the ad must be in ile moe ote that outsie the secifie calibration rane calibration is ossible but the erformance may erae see the system calibration section in able
ad7739 rev. 0 | page 31 of 32 0.1 p f + 10 p f adr421 av dd av dd + 10 p f 0.1 p f av dd clock generator mclkin mclkout 33pf 33pf 6.144mhz dv dd + 10 p f 0.1 p f dv dd 24-bit 6 - ' adc buffer ad7739 ain7 mux aincom ain0 serial interface and control logic sclk din dout cs rdy reset refin( - ) refin(+) dgnd agnd host system analog inputs dv dd 0.1 p f 0.1 p f 0.1 p f 0.1 p f 100 : 100 : 100 : figure 28. typical connections for the ad7739 application
ad7739 rev. 0 | page 32 of 32 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards ms-153ad 0.10 coplanarity figure 29. 24-lead thin shrink small outline pack age [tssop] (ru-24)?dimensions shown in millimeters esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description package outline AD7739BRU ?40c to +105c tssop-24 ru-24 AD7739BRU-reel ?40c to +105c tssop-24 ru-24 AD7739BRU-reel7 ?40c to +105c tssop-24 ru-24 ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. c03742?0?5/03(0)

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